Traditionally, the long, and often tedious, process of digital logic design was carried out by hand. Using a variety of design techniques or heuristic methods, designers constructed logic circuits from available design components. Depending on the task at hand, these design components could be low level components such as transistors, flip-flops or logic gates (e.g., AND gates, OR gates, and NOT gates), higher level components such as counters, multiplexers, random access memories (RAMs), or even microprocessors, or a combination of high and low level components. The designer also had a choice between logic components that performed the same overall function, but that operated at different speeds or that consumed less energy.
Increasingly, however, designers of digital logic rely on computer aided design ("CAD") programs, such as "Design Compiler," by Synopsys, Inc. of Mountain View, Calif., to assist in the synthesis of logic circuits. Using CAD programs, designers can design digital logic circuits using a hardware description language instead of working with discrete logic components. Hardware description languages allow the designer to specify the operation of a logic circuit in software. More specifically, designers specify the flow of signals within the circuitry and the logic functions performed on those signals. Presently, this type of program is written at the so-called "data flow level." Once the designer has programmed the operation of the logic circuit, the CAD program analyzes the program and synthesizes the corresponding logic circuit. The CAD program determines the appropriate logic components and interconnections between components to realize a circuit that satisfies the data flow model. CAD programs are also frequently used to analyze and optimize the performance of gate-level designs. In that case, the input to the CAD program is a gate level design description, as opposed to a data flow level description. The CAD program analyzes the gate level design and synthesizes an improved gate level design.
The synthesized or analyzed logic blocks are often interconnected with other logic blocks to form larger digital logic circuits. However, an important consideration in interconnecting logic blocks is the timing constraints at the interface of the blocks. For example, assume that each of the logic blocks B1, B2, and B3 of FIG. 1 is a block of digital logic to be synthesized or an existing gate level design to be analyzed by a CAD program, and that the blocks are to be interconnected as shown. Block B2 receives signals from block B1, and sends signals to block B3. To choose the correct kind and type of components for the blocks, it is necessary to know how fast block B2 can expect to receive signals from block B1, and how long it will take block B2 to process those signals before passing them to block B3. In other words, it is necessary to determine the time constraints at the boundaries of the blocks.
Traditional CAD programs determine time constraints by performing a static timing analysis using a single simulation of the data flow or gate level description of the logic circuit. Static timing analysis finds all the possible timing paths in the circuit through an exhaustive search, and then calculates the timing values of signals on each path to determine if the signal of any path will cause a timing violation (i.e., circuit malfunction). Based on this simulation, the CAD program synthesizes or refines the logic blocks using logic components and interconnections appropriate to the time constraints.
This technique, however, does not always provide accurate timing data. The time it takes logic circuits to process signals depends on various factors, such as the path the signals take through the logic circuit, whether the digital signals are transitioning from high to low versus low to high, and what mode the circuit is operating in. If the circuit is operating in conjunction with a RAM, for example, signals will be processed at different speeds when the circuit is writing to the RAM or reading from the RAM. Moreover, during a static timing analysis, the CAD program does not know the actual circuit state. It therefore assumes the worst case scenario to calculate the timing delay values and the signal timing of each path. The worst case scenario, however, may include analyses of a number of false paths, paths that never occur in real circuit operation. Using a single simulation to obtain timing constraints, current CAD programs do not account for these possible timing variations. Thus, the corresponding synthesized logic circuit may not operate correctly under all operating conditions.
In light of the foregoing, there is a need for a method and system to determine timing constraints from timing data that accurately captures the different operating conditions of a digital logic circuit.